1. Field of the Invention
The present invention relates to counters and more particularly to dynamically latched up/down counters.
2. Description of the Related Art
A high-speed, low power up/down counter is a fundamental component used in many applications, for example, statistics collections circuits, down-sampling circuits, and clock-data-recovery circuits in various communications channels. One conventional approach to achieve a high-speed counter is to partition a synchronous N-bit counter into multiple smaller counters (sub-counter blocks) in a pipeline fashion. Each sub-counter block is supplied with a clock signal which is gated by a control signal. Such a control signal is typically generated using an adjacent less-significant block so as to reduce power consumption. However, such an approach often requires more complex circuitry because of the gated clock overhead, and also consumes more power than an asynchronous approach.
Another known approach is to build an asynchronous (or ripple) counter. Ripple counters are especially useful in applications in which latency is not an issue. In a ripple counter an output of a flip-flop at the n-th bit position is connected to the clock input of a flip-flop at the (n+1)th bit position. Positive edge-triggered flip-flops are used for a down counter, and negative edge-triggered flip-flops are used for an up counter. However, known ripple counters can not count both up and down.
Many known counter designs only count up or down given an input stimulus, typically the system clock. These designs focus on making the fastest counters possible. A few solutions optimize the serial counter while others try to bypass the ripple generation.
Other known counter designs include up/down counters. These counters often require at least two inputs (up or down, among others) to count. One known up/down counter solution implements the counting serially. One possible disadvantage of a serial counter relates to the carry propagation delay when generating a count. The larger the counter (i.e., the more bits generated by the counter), the longer the total delay of the counter.
Accordingly, it would be desirable to provide an up/down counter that is both high performance and low power.